1. Field of the Invention
The invention disclosed herein relates generally to the device layout and packaging configuration of power MOSFETs. More particularly, this invention relates to a novel and improved device layout and packaging configuration for fabricating and connecting power MOSFETs within electronic packages to achieve high speed switching, reduced power consumption and improved heat dissipation.
2. Description of the Prior Art
Conventional device layout and packaging configurations for fabricating and connecting a power metal-oxide semiconductor field effect transistor (MOSFET) within an electronic package suffer from parasitic effects such as source inductance Ls and gate resistance Rg which begin to dominate device switching behavior in high frequency applications >200 kHz. For a switched mode power supply, improvements in performance have been made for a power MOSFET by carefully optimizing the tradeoff between the conduction and switching losses. However, switching losses increase significantly when the induced device parasitic effects become more prominent. There are ever-increased demands to improve upon the conventional device layout and packaging configurations now commonly implemented for the power MOSFET to achieve faster switching operations with reduced power dissipation when the MOSFETs are used for higher frequency operation.
Recent advancements made in silicon technology allow for very low on-resistance power MOSFETs; small low-cost chips may be implemented to carry very high power densities. However, the small device area usually leads to high thermal resistance, and higher operating temperatures, because the heat is dissipated in a small area. Moreover, package parasitic inductance may become worse, since with small die there is only room for a few bond wires, spaced closer together. Thus, more heat will be dissipated in the MOSFET. This problem becomes more severe as lower device resistances and improved technology allow for higher operating currents for the same package size because the effect of parasitic inductance increases with operating current. Clearly, there is a need to reduce parasitic inductance, which in turn leads to lower power dissipation in the MOSFET. The gate resistance of a MOSFET slows down the switching speed of the MOSFET, also leading to higher power loss, and must therefore be minimized.
To present a clear contrast between the prior art configuration and that of the present invention, the example of a prior art SOIC8 package is first described as that shown in FIG. 1A. However, as will be described below the new and improved configuration of this invention is applicable to a wide variety of electronic packages other than the SOCI8 package. FIG. 1A shows a typical power MOSFET package 10 which includes a MOSFET device 15, i.e., the chip, connected to lead frames 20 by the use of wires 25, e.g., gold wires with a diameter of approximately 2 mils. A MOSFET device 15 that has a large area is commonly fabricated and applied that includes a plurality of gate-metal stripes, i.e., the gate buses 30. The gate buses 30 divide the source contact surface into several areas, and are needed to reduce gate resistance. The wires 25 are formed to connect the lead frames 20 to the surface of source contact. For the convenience of fabrication and cost savings, the wires 25 are formed to dispose on the source contact surface near the lead frames 20 such that the wires are shorter and easier to maneuver in the wiring processes. A separate gate contact 40 is also provided connected to the lead frame with a conductive gate wire 45. FIG. 1B shows the same device in a package where the source leads are not fused together to a single lead frame. The examples of a power MOSFET in an SOIC8 package as shown in the FIGS. 1A and 1B are typical configurations commonly implemented in the industry. The MOSFET chip as shown has a relatively large die size and then the die is segmented with the gate buses to reduce gate resistance. For the purpose of resolving the technical difficulties by reducing the gate resistance, source inductance and inductance induced power dissipations, two smaller MOSFET chips are arranged in parallel within the package as that shown in FIGS. 2A and 2B. However, the gate wires 45 as shown limit the source bondable areas for one of the devices. Only a few wires 25 may be used for the low die as that shown in FIG. 2A. A longer gate wire 45 is required, thus unduly increasing the gate resistance. In FIG. 2B, the layout is improved to accommodate more source wires 25 for the lower die, but now the source wires for the upper die are longer, as is the gate wire, leading to excessive parasitic inductance. Furthermore, in both FIGS. 2A and 2B a rotation of one die is required with respect to the other, resulting in two passes through the assembly process. If the two die were to be segmented by gate buses, as in FIGS. 1A and 1B, the source wires could not be evenly distributed over the source bonding areas of these die, which would inhibit the use of gate buses, and thereby penalize gate resistance.
As explained above, in addition to a design goal of reducing the package resistance, there is a need to reduce the inductance to reduce power dissipation for a MOSFET device when it is used to switch high currents at high frequencies. Therefore, a need still exists in the art to provide an improved layout and packaging configuration to resolve these difficulties.